Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Digital systems engineering
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Proceedings of the 37th Annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fault-aware communication mapping for NoCs with guaranteed latency
International Journal of Parallel Programming
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Although digital circuits are inherently immune to most sources of noise, the scaling of supply voltages and MOSFET threshold voltages has resulted in lowered noise margins. Most CMOS circuits continue to have considerable immunity to power supply and substrate noise even with the aggressive scaling used today. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits. Compounding these problems is the fact that there are very few, if any, reliable tools for detecting coupling noise on large and complex digital circuits.This paper discusses the coupling noise analysis method used during the development of the UltraSPARC-III microprocessor. A good noise analysis strategy should not only pick out the noise violations in a design but also be robust enough to run a sensitivity analysis, with the aim of recommending solutions to the problems found. The model presented places emphasis on its scalability to large datasets, such as the design database of modern high performance microprocessors, comprising of several million transistors. A hierarchical approach to achieve this is proposed and the capacity achieved is illustrated with results on real circuits.