DAC '96 Proceedings of the 33rd annual Design Automation Conference
Bounds for BEM capacitance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast hierarchical algorithm for 3-D capacitance extraction
DAC '98 Proceedings of the 35th annual Design Automation Conference
Boundary element method macromodels for 2-D hierachical capacitance extraction
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-order Nyström schemes for efficient 3-D capacitance extraction
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Parasitic extraction accuracy; how much is enough? (panel)
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A multiscale method for fast capacitance extraction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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This paper presents a practical approach to parasitic extraction enabling accurate timing and crosstalk analyses throughout the design cycle. New error indexes, are first proposed for evaluating the accuracy of flat parasitic extraction. The requirements for extraction in hierarchical design flows are then discussed. The methodology reported aims at reducing the gap between the parasitic values estimated with incomplete design and the results of post-layout extraction. The objective is to obtain consistent interconnect models in top-down and bottom-up design flows. This methodology was integrated into the design flow for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.