The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient dynamic circuit design in the presence of crosstalk noise
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Predicting coupled noise in RC circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
Dynamic Noise Analysis with Capacitive and Inductive Coupling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
False-Noise Analysis for Domino Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delay noise pessimism reduction by logic correlations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Constrained aggressor set selection for maximum coupling noise
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs.