Dynamic Noise Analysis with Capacitive and Inductive Coupling

Authors:
Seung Hoon Choi;Bipul C. Paul;Kaushik Roy
Affiliations:
School Of Electrical And Computer Engineering, Purdue University, W. Lafayette, IN;School Of Electrical And Computer Engineering, Purdue University, W. Lafayette, IN;School Of Electrical And Computer Engineering, Purdue University, W. Lafayette, IN
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 5
Cited 5

A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits

DAC '98 Proceedings of the 35th annual Design Automation Conference
Dynamic noise analysis in precharge-evaluate circuits

Proceedings of the 37th Annual Design Automation Conference
Interconnect tuning strategies for high-performance ICs

Proceedings of the conference on Design, automation and test in Europe
Electric Circuits

Electric Circuits

A New Crosstalk Noise Model for DOMINO Logic Circuits

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Generating realistic stimuli for accurate power grid analysis

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Semi-random net reordering for reducing timing variations and improving signal integrity

Microelectronics Journal
Realistic scalability of noise in dynamic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however, for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. Design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.