Interconnect design with VLSI CMOS
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
A roadmap of CAD tool changes for sub-micron interconnect problems
Proceedings of the 1997 international symposium on Physical design
Physical design challenges for performance
Proceedings of the 1997 international symposium on Physical design
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Futures for partitioning in physical design (tutorial)
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic noise analysis in precharge-evaluate circuits
Proceedings of the 37th Annual Design Automation Conference
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Wave pipelining for application-specific networks-on-chips
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Minimum-buffered routing of non-critical nets for slew rate and reliability control
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the 40th annual Design Automation Conference
Dynamic Noise Analysis with Capacitive and Inductive Coupling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Designing fast on-chip interconnects for deep submicrometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Formal derivation of optimal active shielding for low-power on-chip buses
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Contango: integrated optimization of SoC clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
Realistic scalability of noise in dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design tools for artificial nervous systems
Proceedings of the 49th Annual Design Automation Conference
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
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Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We ad-dress four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.