A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 international symposium on Physical design
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
The future of clock network synthesis
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for improvement through better CAD algorithms and tools. Our work offers new algorithms and a methodology for SPICE-accurate optimization of clock networks, coordinated to satisfy slew constraints and achieve best trade-offs between skew, insertion delay, power, as well as tolerance to variations. Our implementation, called Contango, is evaluated on 45nm benchmarks from IBM Research and Texas Instruments with up to 50K sinks.