Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Contango: integrated optimization of SoC clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Buered clock tree synthesis (CTS) is increasingly critical as VLSI technology continually scales down. Many researches have been done on this topic due to its key role in CTS, but current approaches either lack the obstacle-avoiding functionality or lead to large clock latency and/or skew. This paper presents a new obstacle-avoiding CTS approach with separate clock tree construction and buer insertion stages based on an integral view to explore the global optimization space. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buer positions, and a fast heuristic buer insertion algorithm. Experimental results show the eectiveness of our CTS approach with significantly improved skew and latency than [6] by 46% and 63% on average, and 15.3% reduction in skew than [5]. Our OBB heuristic obtains 36% improvement in skew than the classic balanced bipartition algorithm (BB) in [10].