Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
More practical bounded-skew clock routing
DAC '97 Proceedings of the 34th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Clustering and load balancing for buffered clock tree synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient implementation of a planar clock routing with the treatment of obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
Top-down-based symmetrical buffered clock routing
Proceedings of the great lakes symposium on VLSI
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In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The nominal clock skew always plays a crucial role in determining circuit performance and thus should be a first-order objective for clock-tree synthesis. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the major optimization objective to measure the effects of process variation on clock-tree synthesis. In this paper, we propose a three-level framework which effectively constructs clock trees by performing blockageavoiding buffer insertion with both nominal skew and CLR minimization. To cope with the objectives, we present a novel three-stage TTR clock-tree construction algorithm which consists of clock-tree Topology Generation, Tapping-Point Determination, and Routing. Experimental results show that our framework with the TTR algorithm achieves the best average quality for both nominal skew and CLR, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest.