Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2009 international symposium on Physical design
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Low-power anti-aging zero skew clock gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Buffers in clock trees introduce two additional sources of skew: the first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.