Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Clustering and load balancing for buffered clock tree synthesis
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NBTI effects on tree-like clock distribution networks
Proceedings of the great lakes symposium on VLSI
Low-power anti-aging zero skew clock gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0--1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.