Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and optimization of NBTI induced clock skew in gated clock trees
Proceedings of the Conference on Design, Automation and Test in Europe
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Negative Bias Temperature Instability (NBTI) is considered one of the most critical device reliability concerns in nanometer CMOS technologies, because it causes devices to exhibit a temporal drift of performance over time. In this work, we analyze the effects of this aging mechanism on tree-based Clock Distribution Networks (CDNs). Aging on clock tree can in fact impact the skew, causing a time-dependent failure of the circuit, if the aging conditions in different portions of the clock tree are non-uniform, like it happens in gated-clock tree in which one portion of the clock tree is selectively disabled to save power. Characterization results collected through an in-house aging simulation framework provide valuable insights on the potential effects of various design parameters such as sizing and fanout of clock buffers and height of clock-trees.