Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge Recycling in Power-Gated CMOS Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
NBTI-aware power gating design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
NBTI mitigation by giving random scan-in vectors during standby mode
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
NBTI effects on tree-like clock distribution networks
Proceedings of the great lakes symposium on VLSI
Alleviating NBTI-induced failure in off-chip output drivers
Proceedings of the great lakes symposium on VLSI
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Negative Bias Temperature Instability (NBTI) has been regarded as most important source of reliability of CMOS devices, and specifically pMOS transistors. In this work we focus on the NBTI-induced degradation of sleep transistor cells More in details we present a practical SPICE-based analysis framework for evaluating delay degradation of power-gated circuits due to NBTI-induced current capability reducing of pMOS sleep transistor. We also describe three NBTI-tolerant pMOS sleep transistor cell design approaches, in which the Vith increase due to NBTI is compensated through (i) sleep-transistor over-sizing, (ii) forward-body-biasing, (iii) equivalent 0-probability reduction of the sleep-transistor driving signal. Characterization results on a commercial 45nm CMOS technology define fundamental guide-lines to be used during NBTI-aware sleep-transistor design, while experiments on an industrial benchmark highlight the importance of considering NBTI effect on pMOS sleep transistor design, emphasizing the effectiveness of the proposed design methodologies: more than 85% of time-life extension.