Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Proceedings of the 2009 International Conference on Computer-Aided Design
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
NBTI-aware design of NoC buffers
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Sensor-wise methodology to face NBTI stress of NoC buffers
Proceedings of the Conference on Design, Automation and Test in Europe
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A header-based power gating structure inserts PMOS as sleep transistors between the power rail and the circuit. Since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI) influences the lifetime reliability of PMOS sleep transistors seriously. To tolerate NBTI effect, sizes of PMOS sleep transistors are normally over-sized. In this paper, we propose a novel NBTI-aware power gating architecture to extend the lifetime of PMOS sleep transistors. In our structure, sleep transistors are switched on/off periodically so that overall turned-on times of sleep transistors are reduced and sleep transistors are less influenced by NBTI effect. The experimental results show that our approach can achieve better lifetime extensions of PMOS sleep transistors than previous works and few area overheads.