An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon

Authors:
Yu-Ting Chen;Da-Cheng Juan;Ming-Chao Lee;Shih-Chieh Chang
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

Citing 5
Cited 10

Understanding and minimizing ground bounce during mode transition of power gating structures

Proceedings of the 2003 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges in sleep transistor design and implementation in low-power designs

Proceedings of the 43rd annual Design Automation Conference
Timing driven power gating

Proceedings of the 43rd annual Design Automation Conference
A robust power gating structure and power mode transition strategy for MTCMOS design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

Proceedings of the 13th international symposium on Low power electronics and design
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits

IEEE Transactions on Circuits and Systems Part I: Regular Papers
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs

Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wakeup synthesis and its buffered tree construction for power gating circuit designs

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
NBTI-aware power gating design

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Comprehensive analysis and control of design parameters for power gated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs

Proceedings of the International Conference on Computer-Aided Design
Power-up sequence control for MTCMOS designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the surge current during the power mode transition for the Distributed Sleep Transistor Network (DSTN) designs. Based on these properties, we propose an accurate estimation of surge current and provide an efficient schedule on the DSTN structure. Our experiment achieved significantly better results than previous works---on average, 332 times wake-up time reduction and 35.48% less energy loss during the power mode transition.