Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
Sleep transistor sizing and control for resonant supply noise damping
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Proceedings of the 13th international symposium on Low power electronics and design
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
Coarse-grain MTCMOS sleep transistor sizing using delay budgeting
Proceedings of the conference on Design, automation and test in Europe
Optimal MTCMOS reactivation under power supply noise and performance constraints
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing driven power gating in high-level synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comprehensive analysis and control of design parameters for power gated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heurists for minimizing the sizes of sleep transistors. Our experimental results are very exciting.