IEEE Transactions on Computers
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing analysis and optimization of sequential circuits
Timing analysis and optimization of sequential circuits
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
| Hi-index | 0.00 |
The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.