REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Early planning for clock skew scheduling during register binding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimal voltage assignment approach for low power using ILP
WSEAS Transactions on Circuits and Systems
Timing driven power gating in high-level synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimal dual voltage assignment algorithm for low power under timing-constraints
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Minimum-period register binding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D area-aware partitioning for floorplanner
CSS'11 Proceedings of the 5th WSEAS international conference on Circuits, systems and signals
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In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimum-period register binding solution. Experimental data show that, in most benchmark circuits, the lower bound of the clock period can be achieved without any extra overhead on the number of registers.