REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory segmentation to exploit sleep mode operation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
A high-level register optimization technique for minimizing leakage and dynamic power
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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This paper presents a register binding algorithm in high level synthesis with the objective of register minimization. Our main observation is that not all pipelined functional units are operating at all time. Idle pipelined functional units can be used to store data temporarily, reducing stand-alone registers. The proposed register binding scheme is applied to a suite of benchmark circuits. Experimental results demonstrate that register counts can be lowered by 20% on average in comparison to the left-edge algorithm [10], which is often considered as the optimal approach. Our optimized circuits are synthesized, placed, and routed using state-of-the-art industrial EDA tools. The reduction of register leads to 31% and 23% decrease in rising and falling clock skews, respectively. Moreover, the benchmark circuits have 7% less total wirelength with a 4% power reduction on average.