Memory segmentation to exploit sleep mode operation

Activity-driven clock design for low power circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low energy memory and register allocation using network flow

DAC '97 Proceedings of the 34th annual Design Automation Conference

Power optimization for FPGA look-up tables

Proceedings of the 1997 international symposium on Physical design

Transforming control-flow intensive designs to facilitate power management

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

System-level power optimization: techniques and tools

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Behavioral-level partitioning for low power design in control-dominated application

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

System-level power optimization: techniques and tools

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A predictive system shutdown method for energy saving of event-driven computation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A recursive algorithm for low-power memory partitioning

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

From architecture to layout: partitioned memory synthesis for embedded systems-on-chip

Proceedings of the 38th annual Design Automation Conference

Layout-driven memory synthesis for embedded systems-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reducing access energy of on-chip data memory considering active data bitwidth

Proceedings of the 2002 international symposium on Low power electronics and design

Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques

ACM Transactions on Embedded Computing Systems (TECS)

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation

IEEE Design & Test

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

Journal of VLSI Signal Processing Systems

Synthesis of low-power selectively-clocked systems from high-level specification

ISSS '96 Proceedings of the 9th international symposium on System synthesis

Nonuniform Banking for Reducing Memory Energy Consumption

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Power-aware RAM mapping for FPGA embedded memory blocks

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Better than optimum?: register reduction using idle pipelined functional units

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Power optimization with power islands synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Algorithmic techniques for memory energy reduction

WEA'03 Proceedings of the 2nd international conference on Experimental and efficient algorithms