Power-aware RAM mapping for FPGA embedded memory blocks

Authors:
Russell Tessier;Vaughn Betz;David Neto;Thiagaraja Gopalsamy
Affiliations:
University of Massachusetts;Altera Toronto Technology Centre, Toronto, ON, Canada;Altera Toronto Technology Centre, Toronto, ON, Canada;Altera Corporation, San Jose, CA
Venue:
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Year:
2006

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Abstract

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.