Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Definition and solution of the memory packing problem for field-programmable systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Fault-tolerant resynthesis with dual-output LUTs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test cases while an existing greedy method could do so only for about one third of the test cases.