Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The Soft Error Problem: An Architectural Perspective
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Architecture-specific packing for virtex-5 FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A generalized network flow based algorithm for power-aware FPGA memory mapping
Proceedings of the 45th annual Design Automation Conference
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
Proceedings of the 47th Design Automation Conference
SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
In-place decomposition for robustness in FPGA
Proceedings of the International Conference on Computer-Aided Design
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We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this architectural feature can be used to build redundancy for fault masking with limited area and performance over-head. Our algorithm improves reliability of a mapping by performing two basic operations: duplication (in which free configuration bits are used to duplicate a logic function whose value is obtained at the secondary output) and encoding (in which two copies of the same logic function are ANDed or ORed together in the fanout of the duplicated logic). The problem of fault tolerant post-mapping resynthesis is then formulated as the optimal duplication and encoding scheme that ensures the minimal circuit fault rate w.r.t. a stochastic single fault model. We present an ILP formulation of this problem and an efficient algorithm based on generalized network flow. On MCNC benchmarks, experimental results show that for combinational circuits the proposed approach improves meantime- to-failure(MTTF) by 27% with 4% area overhead, and the proposed approach with explicit area redundancy improves MTTF by 113% with 36% area overhead, compared to the baseline mapping by ABC. This provides a viable fault tolerance solution for non-mission critical applications compared to TMR (triple modular redundancy) which has a 5x--6x area overhead.