Architecture-specific packing for virtex-5 FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Architecture Design for Soft Errors
Architecture Design for Soft Errors
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Fault-tolerant resynthesis with dual-output LUTs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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The programmable logic block (PLB) in a modern FPGA features a built-in carry chain (or adder) and a decomposable LUT, where such an LUT may be decomposed into two or more smaller LUTs. Leveraging decomposable LUTs and underutilized carry chains, we propose to decompose a logic function in a PLB into two subfunctions and to combine the subfunctions via a carry chain to make the circuit more robust against single-event upsets(SEUs). Note that such decomposition can be implemented using the decomposable LUT and carry chain in the original PLB without changing the PLB-level placement and routing. Therefore, it is an in-place decomposition (IPD) with no area and timing overhead at the PLB level and has an ideal design closure between logic and physical syntheses. For 10 largest combinational MCNC benchmark circuits with a conservative 20% utilization rate for carry chain, IPD improves MTTF (mean time to failure) by 1.43 and 2.70 times respectively, for PLBs similar to those in Xilinx Virtex-5 and Altera Stratix-IV.