Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Post-route LUT output polarity selection for timing optimization
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
A Linear Programming Approach to Max-Sum Problem: A Review
IEEE Transactions on Pattern Analysis and Machine Intelligence
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 47th Design Automation Conference
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
In-place decomposition for robustness in FPGA
Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Modern SRAM-based FPGAs (Field Programmable Gate Arrays) use multiplexer-based unidirectional routing, and SRAM configuration cells in these multiplexers contribute to the majority of soft errors in FPGAs. In this paper, we formulate an In-Placed inVersion (IPV) on LUT (Look-Up Table) logic polarities to reduce the Soft Error Rate (SER) at chip level, and reveal a locality and NP-Hardness of the IPV problem. We then develop an exact algorithm based on the binary integer linear programming (ILP) and also a heuristic based on the simulated annealing (SA), both enabled by the locality. We report results for the 10 largest MCNC combinational benchmarks synthesized by ABC and then placed and routed by VPR. The results show that IPV obtains close to 4x chip level SER reduction on average and SA is highly effective by obtaining the same SER reduction as ILP does. A recent work IPD has the largest LUT level SER reduction of 2.7x in literature, but its chip level SER reduction is merely 7% due to the dominance of interconnects. In contrast, SA-based IPV obtains nearly 4x chip level SER reduction and runs 30x faster. Furthermore, combining IPV and IPD leads to a chip level SER reduction of 5.3x. This does not change placement and routing, and does not affect design closure. To the best of our knowledge, our work is the first in-depth study on SER reduction for modern multiplexer-based FPGA routing by in-placed logic re-synthesis.