Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Technology mapping for FPGAs with nonuniform pin delays and fast interconnections
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Introduction to Algorithms
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
The effect of post-layout pin permutation on timing
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A 65nm flash-based FPGA fabric optimized for low cost and power
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
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Modern FPGA architectures support flexible polarity propagation in the fabric of logic blocks and interconnects. For example, the output of a lookup-table (LUT) logic block can be inverted by inverting all the bits in the LUT table. The rise and fall delays in either a LUT or a routing multiplexer usually differ substantially. The flexibility of polarity propagation and the difference between the rise and fall delays provide an opportunity to further optimize timing. This paper describes an algorithm to minimize the longest path delay by adjusting LUT output polarity after routing. The algorithm can be extended to reduce active leakage power in routing multiplexers while meeting timing constraints. The algorithm is efficient,easy to implement, and does not require change in placement and routing. Preliminary experiments show that the algorithm can reduce the longest path delay by up to 5.8% and on average 2.5% on a set of customer designs.