Acyclic multi-way partitioning of Boolean networks

Multi-way VLSI circuit partitioning based on dual net representation

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Parallel logic level simulation of VLSI circuits

WSC '94 Proceedings of the 26th conference on Winter simulation

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

EURO-DAC '94 Proceedings of the conference on European design automation

Simultaneous depth and area minimization in LUT-based FPGA mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Parallel gate-level circuit simulation on shared memory architectures

PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation

Actor based parallel VHDL simulation using time warp

PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation

Partitioning of VLSI circuits and systems

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Hierarchical partitioning

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Perils and pitfalls of parallel discrete-event simulation

WSC '96 Proceedings of the 28th conference on Winter simulation

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A multidimensional study on the feasibility of parallel switch-level circuit simulation

Proceedings of the eleventh workshop on Parallel and distributed simulation

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

DAC '98 Proceedings of the 35th annual Design Automation Conference

Shared memory implementation of a parallel switch-level circuit simulator

PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation

Exact and approximate estimation for maximum instantaneous current of CMOS circuits

Proceedings of the conference on Design, automation and test in Europe

Performance driven multiway partitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Clustering based acyclic multi-way partitioning

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Performance-driven technology mapping with MSG partition and selective gate duplication

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Post-route LUT output polarity selection for timing optimization

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Exploiting local logic structures to optimize multi-core SoC floorplanning

Proceedings of the Conference on Design, Automation and Test in Europe

A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning

ACM Transactions on Reconfigurable Technology and Systems (TRETS)