DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Design of Parity Testable Combinational Circuits
IEEE Transactions on Computers
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exploiting signal flow and logic dependency in standard cell placement
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
PLA based synthesis and testing of hazard free logic
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Exact probabilistic analysis of error detection for parity checkers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Computing the area versus delay trade-off curves in technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using cone structures for circuit partitioning into FPGA packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, technology mapping is done by first partitioning a circuit into a forest of trees. Each individual tree is then mapped using dynamic programming. The links among the mappings of different trees are provided via propagating the essential mapping information along multiple fanout branches. While this approach may achieve optimality within each tree, the overall result is compromised from the very first treatment of fanouts. In this article, we propose a new scheme that greatly improves technology mapping. Instead of a forest of trees, we partition the circuit into a set of maximal super-gates (MSGs). These are used to transform the original circuit into trees. We then apply the dynamic programming technique to the trees and allow duplication of gates in the mapping of each individual MSG. Experimental results on ISCAS'85 benchmarks show that our approach delivers an average of 20.6% reduction in delay with only a 9.5% increase on area.