IEEE Transactions on Computers
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Testing of non-feedback bridging faults
Integration, the VLSI Journal
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
On the testing, reliability analysis, and synthesis of combinational circuits (vlsi)
On the testing, reliability analysis, and synthesis of combinational circuits (vlsi)
A Characterization of Binary Decision Diagrams
IEEE Transactions on Computers
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.98 |
Algorithms for the following two problems are presented: (1) computing detection probability of stuck-at faults (CDP), and (2) computing signal probability (CSP). These problems arise in the context of random testing, pseudorandom testing, and testability analysis of combinational circuits. The algorithm for CDP combines the notion of supergates and a refinement of th algorithm for CDP presented in the work of S. Chakravarty and H.B. Hunt, III (1986). The algorithm for CDP can be used to compute the exact value of detection probability of multiple stuck-at faults in circuits with multiple outputs. Single-input, single-output pseudo gates are inserted to model stuck-at faults and derive an equivalent single-output circuit. CDP is thus reduced to the problem of computing the probability distribution of the output over the set of four logic values (0, 1d, d). The algorithm for CDP uses an efficient enumeration algorithm. The authors show how the enumeration algorithm can be used to refine the algorithm for CSP.