Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
IEEE Design & Test
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
IEEE Transactions on Computers
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To predict the difficulty of testing a wire stuck-atfault, testability analysis algorithms provide an estimatedtestability value by computing controllabilityand observability. In all previous work, signal correlationbetween controllability and observability is generallyignored. As a result, the estimated value can beinaccurate. This paper discusses an efficient method totake into account signal correlation for testabilityanalysis. Our experimental results have shown that,with little run time overhead, significant improvementof testability analysis can be achieved.