A two-level guidance heuristic for ATPG
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Algorithms for Automatic Test-Pattern Generation
IEEE Design & Test
RIDDLE: A Foundation for Test Generation on a High-Level Design Description
IEEE Transactions on Computers
An efficient delay test generation system for combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
EST: The new frontier in automatic test-pattern generation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A transitive closure based algorithm for test generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Speed up of behavioral A.T.P.G. using a heuristic criterion
DAC '93 Proceedings of the 30th international Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
An efficient algorithm for local don't care sets calculation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
A Functional Decomposition Method for Redundancy Identification and Test Generation
Journal of Electronic Testing: Theory and Applications
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient Boolean division and substitution
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
CATAPULT: concurrent automatic testing allowing parallelization and using limited topology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integrating symbolic techniques in ATPG-based sequential logic optimization
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Concurrent D-algorithm on reconfigurable hardware
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ATPG-based logic synthesis: an overview
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Generation of search state equivalence for automatic test pattern generation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design for Primitive Delay Fault Testability
ITC '97 Proceedings of the 1997 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Integration, the VLSI Journal
Accelerated test pattern generation by cone-oriented circuit partitioning
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A fast algorithm for finding common multiple-vertex dominators in circuit graphs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
Hierarchical diagnosis of multiple faults
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Node addition and removal in the presence of don't cares
Proceedings of the 47th Design Automation Conference
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
Leveraging dominators for preprocessing QBF
Proceedings of the Conference on Design, Automation and Test in Europe
Rewiring using IRredundancy removal and addition
Proceedings of the Conference on Design, Automation and Test in Europe
A scalable method for the generation of small test sets
Proceedings of the Conference on Design, Automation and Test in Europe
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fast node merging with don't cares using logic implications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On applying erroneous clock gating conditions to further cut down power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Sequential diagnosis by abstraction
Journal of Artificial Intelligence Research
Debugging with dominance: on-the-fly RTL debug solution implications
Proceedings of the International Conference on Computer-Aided Design
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.01 |
The automatic generation of tests for combinational digital circuits is examined from the standpoint of a guided search through a search space. The limitations of this process, namely the size of the search space and the overall strategy, are identified and methods are presented to reduce the size of the search space as well as produce a more optimal ordering of node assignments. A new algorithm is proposed that uses the smaller search space and the improved ordering for node assignments based on a topological analysis of the circuit. Results are presented indicating that this new algorithm, termed TOPological Search (TOPS), is faster than existing algorithms and also rapidly identifies many redundant faults without search.