CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

Authors:
Rhonda Kay Gaede;Don E. Ross;M. Ray Mercer;Kenneth M. Butler
Affiliations:
Department of ECE, ENS 143, The University of Texas at Austin, Austin, Texas;Microelectronics and Computer, Technology Corporation (MCC), 3500 West Balcones Center Drive, Austin, Texas;Department of ECE, ENS 143, The University of Texas at Austin, Austin, Texas;Department of ECE, ENS 143, The University of Texas at Austin, Austin, Texas
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

This paper deals with an improved algorithm for identifying redundant faults and finding tests for “hard faults” in combinational circuits. A new, concurrent approach is proposed which is based upon the concepts of functional decomposition, explicit representation of fanout stems and the Boolean difference. The data structure to be used is the Binary Decision Diagram as developed by Lee, Akers and Bryant. This algorithm operates as a backend to test generators which use random patterns or heuristics or a combination of the two.