AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
IEEE Transactions on Computers
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Fault Folding for Irredundant and Redundant Combinational Circuits
IEEE Transactions on Computers
CATAPULT: concurrent automatic testing allowing parallelization and using limited topology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
Fanout fault analysis for digital logic circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Hi-index | 14.98 |
Stuck-at faults on primary inputs and fan-out branches are commonly used as target faults in test generation algorithms for combinational circuits. This correspondence shows that these faults may not constitute an adequate set of target faults. A procedure is presented for selecting a set of target faults with the property that the detection of all detectable faults from this set guarantees the detection of all detectable faults in the circuit.