Algebraic Fault Analysis for Constrained Combinational Networks
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
Checkpoint Faults are not Sufficient Target Faults for Test Generation
IEEE Transactions on Computers
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design for Testability A Survey
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
ATWIG, an automatic test pattern generator with inherent guidance
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
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Fault folding is the process of applying test equivalent or test implied relations from a primary output towards the connected primary inputs in order to find a reduced set of faults that cover the set of faults on the intervening network.