Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Introduction to algorithms
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Fault-tolerant computer system design
Fault-tolerant computer system design
A high-frequency custom CMOS S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Modeling and Testing a Critical Fault-Tolerant Multi-Process System
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Diversity techniques for concurrent error detection
Diversity techniques for concurrent error detection
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Failure-Tolerant Sequential Machines with Past Information
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Fault Folding for Irredundant and Redundant Combinational Circuits
IEEE Transactions on Computers
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
Algorithm level re-computing: a register transfer level concurrent error detection technique
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Diversity Techniques for Concurrent Error Detection
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems
IEEE Transactions on Computers
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We describe logic synthesis techniques for designingdiverse implementations of combinational logic circuits inorder to maximize the data integrity of diverse duplexsystems in the presence of common-mode failures. Dataintegrity means that the system either produces correctoutputs or indicates errors when incorrect outputs areproduced. Design diversity has long been used to increasethe data integrity of duplex systems against common-modefailures. The conventional notion of diversity is qualitativeand relies on "independent" generation of "different"implementations. In a recent paper, we presented a metricto quantify diversity among several designs. Our synthesistechniques described in this paper use the diversity metricas a cost function and maximize diversity while reducingthe area overhead of the resulting diverse duplex system.