A quantitative measure of robustness for delay fault testing
EURO-DAC '92 Proceedings of the conference on European design automation
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test Generation for Ground Bounce in Internal Logic Circuitry
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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This paper analyzes the problem of timing related common mode failures in redundant systems. The specific case of duplex systems in the presence of delay faults is analyzed by providing a probabilistic characterization of undetectable errors. PDF simulation was used to evaluate the probability of undetectable errors in conventional duplex systems and in duplex systems making use of a simple kind of data diversity.