On the Implementation of Failure-Tolerant Counters
IEEE Transactions on Computers
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Realization of Fault-Tolerant Machines Linear Code Application
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers
Error detection with latency in sequential circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Realization of fault-tolerant and Fail-Safe sequential machines
IEEE Transactions on Computers
| Hi-index | 14.99 |
A sequential machine must have certain redundant information in order to be capable of correcting error. As past inputs and past states are redundant, a sequential machine with error correction capability is constructable by making use of these elements of past information. This paper describes conditions of state assignments, numbers of required redundant state variables, and estimation of reliability of failure-tolerant sequential machines.