Failure-Tolerant Sequential Machines with Past Information
IEEE Transactions on Computers
| Hi-index | 14.98 |
Abstract A new method of designing and implementing intrinsically failure-tolerant counters with error-correcting state assignments is proposed. Threshold logic elements are used, and state recovery circuitry is united with the flip-flop input logic. A decimal counter built according to this method requires considerably fewer components and has a lower probability of failure at less cost than a diode logic version.