Fault-Tolerant Asynchronous Networks

Authors:
Dhiraj K. Pradhan;Sudhakar M. Reddy
Affiliations:
Department of Electrical Engineering, University of Iowa, Iowa City, Iowa./ System Development Division, IBM Corporation, Poughkeepsie, N.Y. 12602.;Department of Electrical Engineering, University of Iowa, Iowa City, Iowa.
Venue:
IEEE Transactions on Computers
Year:
1973

Citing 8
Cited 5

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Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

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Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV

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Asynchronous State Assignments with Unateness Properties and Fault-Secure Design

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Fault-Tolerant Asynchronous Networks Using Read-Only Memories

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Abstract

The design of fault-tolerant asynchronous networks has been an unsolved problem. In this paper, necessary and sufficient conditions on state assignments for fault-tolerant asynchronous networks are given. Three design techniques, based on Liu's 2so - 1 assignment, Friedman et al.'s (2, 2) separating system, and (2so + 1) assignments, are given for fault-tolerant asynchronous networks. The earlier Liu's upper bound on state variables for USTI assignment for 2so rows is improved to 2so - 2so驴3.