Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Asynchronous Sequential Machines Designed for Fault Detection
IEEE Transactions on Computers
A Fail-Safe Asynchronous Sequential Machine
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Sequential Machines
IEEE Transactions on Computers
Fault Tolerant Sequential Machines
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers
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The design of unrestricted, stuck-at fault tolerant, asynchronous sequential circuits involves the use of complex software. Since software errors might lead to incorrect design, it is important to verify the correctness of the results.A possible method to do this, is by proving that the design possesses the required properties 'unrestricted' and 'stuck-at fault tolerant'. This paper presents this approach using the model checker SMV. The approach used is general, and can be applied to all mealy-type asynchronous sequential circuits.The paper shows the approach using an example. It appears possible to prove that the circuit is unrestricted, does not reach undefined states, is stable, and shows correct behavior. These properties are also proved under the assumption of the presence of one stuck-at fault.An important intermediate result is the design of the delay in the feedback loop of the asynchronous sequential circuit. Since the duration of the time steps in the model checker is random, it is not possible to use a deterministic model. The model developed is an abstract model for the behavior of delay elements comparable to RC-filters. It includes a notion of synchronization with the other delays in the circuit.