A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A new methodology for the design of low-cost fail safe circuits and networks
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
On-Set Realization of Fail-Safe Sequential Machines
IEEE Transactions on Computers
Probability of State Transition Errors in a Finite State Machine Containing Soft Failures
IEEE Transactions on Computers
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Asynchronous Sequential Machines Designed for Fault Detection
IEEE Transactions on Computers
A Fail-Safe Asynchronous Sequential Machine
IEEE Transactions on Computers
A Totally Self-Checking Checker Design for the Detection of Errors in Periodic Signals
IEEE Transactions on Computers
Design of Reliable Synchronous Sequential Circuits
IEEE Transactions on Computers
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Fail-Safe Asynchronous Sequential Machines
IEEE Transactions on Computers
Fail-Safe Asynchronous Machines with Multiple-Input Changes
IEEE Transactions on Computers
Separating and Completely Separating Systems and Linear Codes
IEEE Transactions on Computers
Programmable Array Realizations of Synchronous Sequential Machines
IEEE Transactions on Computers
An overview of fault-tolerant digital system architecture
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Fault-Tolerant Asynchronous Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
Realization of fault-tolerant and Fail-Safe sequential machines
IEEE Transactions on Computers
Hi-index | 15.03 |
A fail-safe sequential machine is one that produces safe-side output when failures occur in the machine. This paper presents a new method of realization of fail-safe sequential machines under the following assumptions: 1) failure is caused by a single fault of element in the machine, 2) output of faulty element is stuck at one or zero, and 3) input does not malfunction.