On-Set Realization of Fail-Safe Sequential Machines
IEEE Transactions on Computers
Asynchronous Sequential Machines Designed for Fault Detection
IEEE Transactions on Computers
State Assignments for Asynchronous Sequential Machines
IEEE Transactions on Computers
Fault-Tolerant Asynchronous Sequential Machines
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
Improved State Assignment Selection Tests
IEEE Transactions on Computers
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Perspective
IEEE Transactions on Computers
Fail-Safe Asynchronous Machines with Multiple-Input Changes
IEEE Transactions on Computers
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Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition theory, is presented. From this method an easily calculated upper bound on the number of gates required-to realize a fail-safe circuit is derived.