IEEE Transactions on Computers
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
N-Fail-Safe Sequential Machines
IEEE Transactions on Computers
A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
A new methodology for the design of low-cost fail safe circuits and networks
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Design of Reliable Synchronous Sequential Circuits
IEEE Transactions on Computers
Fail-Safe Asynchronous Machines with Multiple-Input Changes
IEEE Transactions on Computers
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Fail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C.