Design of Two-Level Fault-Tolerant Networks
IEEE Transactions on Computers
On-Set Realization of Fail-Safe Sequential Machines
IEEE Transactions on Computers
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races
IEEE Transactions on Computers
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Asynchronous Sequential Machines Designed for Fault Detection
IEEE Transactions on Computers
A Fail-Safe Asynchronous Sequential Machine
IEEE Transactions on Computers
Design of Reliable Synchronous Sequential Circuits
IEEE Transactions on Computers
Fail-Safe Asynchronous Sequential Machines
IEEE Transactions on Computers
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory
IEEE Transactions on Computers
Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops
IEEE Transactions on Computers
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
An overview of fault-tolerant digital system architecture
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
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Several synthesis methods for fail-safe asynchronous sequential machines have been reported recently. All of these methods solve the race problem by using noncritical race state assignments. This approach generally results in large number of state variables, relatively complicated design, and the limitation of single-input change.