Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Authors:
Y. Tohma
Affiliations:
Department of Electronics, Tokyo Institute of Technology
Venue:
IEEE Transactions on Computers
Year:
1974

Citing 0
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Abstract

A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.