On-Set Realization of Fail-Safe Sequential Machines
IEEE Transactions on Computers
Design of Reliable Synchronous Sequential Circuits
IEEE Transactions on Computers
Monotone Functions in Sequential Circuits
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
Derivation of Minimal Test Sets for Monotonic Logic Circuits
IEEE Transactions on Computers
A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Fail-Safe Asynchronous Machines with Multiple-Input Changes
IEEE Transactions on Computers
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A method for realization of fail-safe sequential machines, using a class of separable codes called Berger codes in the state assignment, has been presented. The separability property is desirable in certain applications. Both on-set and off-set realizations are used for the next-state functions and this has the advantage over the methods using only on-set realization in that the checker is simpler. Realization of the output circuit is also considered.