Realization Methods for Asynchronous Sequential Circuits
IEEE Transactions on Computers
Universal Single Transition Time Asynchronous State Assignments
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
Asynchronous sequential circuits with (2, 1) type state assignments
SWAT '70 Proceedings of the 11th Annual Symposium on Switching and Automata Theory (swat 1970)
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Design of Fail-Safe Sequential Machines Using Separable Codes
IEEE Transactions on Computers
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Separating and Completely Separating Systems and Linear Codes
IEEE Transactions on Computers
Programmable Array Realizations of Synchronous Sequential Machines
IEEE Transactions on Computers
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper is concerned with the problem of realizing an arbitrary syndconous or asynchronous sequential machine using only monotone AMR (or decreasing) switching functions. It has been found that h ion always exist, that in the asynchronous case only nomal fundamental mode flow tables are considered. Univesl state assignmments resulting in monotone inceasing (or next-state funtions are characterized using the concept of an (i,j) completely separating system.