A Survey of Microcellular Research
Journal of the ACM (JACM)
Cellular arrays for asynchronous control
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
A Cellular Structure for Sequential Networks
IEEE Transactions on Computers
Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals
IEEE Transactions on Computers
Monotone Functions in Sequential Circuits
IEEE Transactions on Computers
Unate Cascade Realization of Synchronous Sequential Machines
IEEE Transactions on Computers
IEEE Transactions on Computers
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers
N-Fail-Safe Sequential Machines
IEEE Transactions on Computers
Cellular Synthesis of Synchronous Sequential Machines
IEEE Transactions on Computers
A Cellular-Array Multiplier for GF(2m)
IEEE Transactions on Computers
Universal logic circuits and their modular realizations
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Iteratively Realized Sequential Circuits
IEEE Transactions on Computers
Generation of near-optimal universal Boolean functions
Journal of Computer and System Sciences
Hi-index | 14.98 |
Cellular-array realizations of switching functions have been studied in order to take advantage of the many design possibilities offered by large-scale integration technology. This paper introduces a class of programmable cellular arrays that can be employed to realize arbitrary synchronous sequential machines. State assignments based upon k-out-of-m codes are employed to give rise to machine excitation and output equations in a consistent functional form suitable for implementation via a cellular structure. The proposed arrays are programmable, which makes possible the capability of re-configuring an array to realize different machines by electronically altering the function implemented by each cell of the array. A synthesis algorithm is presented that will allow the designer to program the array without explicitly deriving excitation and output functions. The synthesis technique is applicable to both Mealy and Moore machines with any number of inputs, outputs, and internal states, and utilizing either delay or trigger flip-flops.