The synthesis of multipurpose logic devices
SWAT '66 Proceedings of the 7th Annual Symposium on Switching and Automata Theory (swat 1966)
The universal logic block (ULB) and its application to logic design
SWAT '66 Proceedings of the 7th Annual Symposium on Switching and Automata Theory (swat 1966)
An Algorithm for Optimal Logic Design Using Multiplexers
IEEE Transactions on Computers
Universal Logic Modules and Their Applications
IEEE Transactions on Computers
A Decomposition Chart Technique to Aid in Realizations with Multiplexers
IEEE Transactions on Computers
On the Design of Universal Boolean Functions
IEEE Transactions on Computers
Comments on "Universal Logic Modules and Their Applications"
IEEE Transactions on Computers
ULM Implicants for Minimization of Univers Logic Module Circuits
IEEE Transactions on Computers
A Numerical Expansion Technique and Its Application to Minimal Multiplexer Logic Circuits
IEEE Transactions on Computers
Programmable Array Realizations of Synchronous Sequential Machines
IEEE Transactions on Computers
Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals
IEEE Transactions on Computers
Sequential Machine Implementations Using Universal Logic Modules
IEEE Transactions on Computers
On the Minimization of Tree-Type Universal Logic Circuits
IEEE Transactions on Computers
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters
IEEE Transactions on Computers
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module
IEEE Transactions on Computers
Diagnosis and utilization of faulty universal tree circuits
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Universal base functions and modules for realizing arbitrary switching functions
IEEE Transactions on Computers
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In order to achieve the great economic advantage of utilizing integrated circuits in computer circuitry, it is desirable to design a circuit which can realize any logic function of a fixed number of variables by simply varying its input terminal connections. Such a circuit is called a universal logic circuit (ULC). When the number of variables becomes large, a ULC may be too complex to be built in a single package economically. Hence, it is preferred to use ULC's of a small number of variables as the modules to build a ULC of a large number of variables. Such modules are called universal logic modules (ULM's). In this paper, we shall first present a three-variable ULC, which has a fan-in for each logic gate not exceeding four, and consists of only 7 I/O pins. Then, we shall extend the ULC's to four or more variables. There are 12 I/O pins in a ULC of four variables, and several models with different fan-in limitations will be given. The logic gates in the ULC's may be all NAND or all NOR gates. Then, a simple technique for designing a ULC of any large number of variables using the ULC's of a small number of variables, say three variables, as the ULM's will be established. It will be seen that the ULC obtained by this technique will require a small number of ULM's. Moreover, the fault-detection tests for ULM's and a diagnostic procedure for locating all the faulty ULM's in the modular realization of a ULC realizing a given logic function will be presented. Finally, a method for improving the reliability of a ULC using an error-correcting code will be demonstrated.