Generation of Primes by a One-Dimensional Real-Time Iterative Array
Journal of the ACM (JACM)
Communications of the ACM
A spatially iterated memory organ patterned after the cerebral cortex
ACM '61 Proceedings of the 1961 16th ACM national meeting
Embedding computers in a cellular array
ACM SIGARCH Computer Architecture News
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates
Journal of the ACM (JACM)
Run-Time defect tolerance using JBits
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
An iteratively structured information processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
A cellular general purpose computer
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Hardware algorithms for nonnumeric computation
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Cellular arrays for asynchronous control
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
Automation techniques for Large Scale Integration system design
ACM '69 Proceedings of the 1969 24th national conference
A Simplified Summation Array for Cellular Logic Modules
IEEE Transactions on Computers
IEEE Transactions on Computers
A System of Magnetic Bubble Logic
IEEE Transactions on Computers
Characterization of Unate Cascade Realizability Using Parameters
IEEE Transactions on Computers
Minimization of Exclusive or and Logical Equivalence Switching Circuits
IEEE Transactions on Computers
Fault Diagnosis and Repair of Cutpoint Cellular Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Logical Networks of Flexible Cells
IEEE Transactions on Computers
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays
IEEE Transactions on Computers
R70-11 Representation of Events in the von Neumann Cellular Model
IEEE Transactions on Computers
The Characterization and Properties of Cascade Realizable Switching Functions
IEEE Transactions on Computers
IEEE Transactions on Computers
Logic Design Using EFL Structures
IEEE Transactions on Computers
Programmable Array Realizations of Synchronous Sequential Machines
IEEE Transactions on Computers
Effective Pipelining of Digital Systems
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
The Questions of Systems Implementation with Large-Scale Integration
IEEE Transactions on Computers
A Cellular Structure for Sequential Networks
IEEE Transactions on Computers
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Large-scale integration from the user's point of view
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
Diagnosis and utilization of faulty universal tree circuits
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Fault location in cellular arrays
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Implementation of the NASA modular computer with LSI functional characters
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Iteratively Realized Sequential Circuits
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
A completeness problem for pattern generation in tessellation automata
Journal of Computer and System Sciences
IEEE Transactions on Computers
Universal base functions and modules for realizing arbitrary switching functions
IEEE Transactions on Computers
Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computing
International Journal of Reconfigurable Computing
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This paper is a survey of research on microcellular techniques. Of particular interest are those techniques that are appropriate for realization by modern batch-fabrication processes, since the rapid emergence of reliable and economical batch-fabricated components represents probably the most important current trend in the field of digital circuits.First the manufacturing methods for batch-fabricated components are reviewed, and the advantages to be realized from the application of the principles of cellular logic design are discussed. Also two categorizations of cellular arrays are made in terms of the complexity of each cell (only low-complexity cells are considered) and in terms of the various application areas.After a survey of very early techniques that can be viewed as exemplifying cellular approaches, modern-day cellular arrays are discussed on the basis of whether they are fixed cell-function arrays or variable cell-function arrays. In the fixed cell-function arrays the switching function produced by each cell is fixed; the cell parameters are used only in the modification of the interconnection structure. Several versions of NOR gate arrays, majority gate arrays, adder arrays, and others are reviewed in terms of synthesis techniques and array growth rates.Similarly, the current status of research is summarized in variable cell-function arrays, where not only the interconnection structure but also the function produced by each cell is determined by parameter selection. These arrays include various general function cascades, outpoint arrays, and cobweb arrays, for example. Again, the various cell types that have been considered are pointed out, as well as synthesis procedures and growth rates appropriate for them.Finally, several areas requiring further research effort are summarized. These include the need for more realistic measures of array growth rates, the need for synthesis techniques for multiple-function arrays and programmable arrays, and the need for fault-avoidance algorithms in integrated structures.