A Survey of Microcellular Research
Journal of the ACM (JACM)
An Augmented Content-Addressed Memory Array for Implementation With Large-Scale Integration
Journal of the ACM (JACM)
Tessellation Aspect of Combinational Cellular Array Testing
IEEE Transactions on Computers
Cellular Interconnection Arrays
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
Checking Experiments ror Sequential Machines
IEEE Transactions on Computers
Iterative Arrays ror Radix Conversion
IEEE Transactions on Computers
Fault detection in a linear cascade of identical machines
SWAT '68 Proceedings of the 9th Annual Symposium on Switching and Automata Theory (swat 1968)
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
A strategy for detecting faults in sequential machines not possessing distinguishing sequences
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Iteratively Realized Sequential Circuits
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Fault Detection in Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The progress of semiconductor technology has been a dominant factor on the use of cellular arrays in digital computer design. When a subsystem is implemented in the form of a cellular array, it is important that the subsystem can be tested at the array terminals for the presence of a faulty cell in the array. In this paper some sufficient conditions for the testability of two-dimensional sequential cellular arrays are derived. These can be either unilaterally interconnected or bilaterally interconnected arrays where each cell has some storage elements and logic circuits.